![]() for OTC and CDROM): 0-15 BC Number of words (0001h.FFFFh) (or 0=10000h words)ġ6-31 0 Not used (usually 0 for OTC, or 1 ("one block") for CDROM)įor SyncMode=1 (ie. Note: Address bit0-1 are writeable, but any updated current/end addresses are Hold the end-address in SyncMode=1, or the end marker in SyncMode=2) The start address of the currently transferred block at transfer end, it'll In SyncMode=1 and SyncMode=2, the hardware does update MADR (it will contain Getting interrupted by a higher priority DMA channel). The start address even during and after the transfer) (unless Chopping isĮnabled, in that case it does update MADR, same does probably also happen when In SyncMode=0, the hardware doesn't update the MADR registers (it will contain 1F801080h+N*10h - D#_MADR - DMA base address (Channel 0.6) (R/W) 0-23 Memory Address where the DMA will start reading from/writing to ![]() Need to initialize an address (and transfer direction, transfer enabled, etc.)Īt the remote-side (eg. 1F801080h+N*10h - D#_MADR - DMA base address (Channel 0.6) (R/W)ġF801084h+N*10h - D#_BCR - DMA Block Control (Channel 0.6) (R/W)ġF801088h+N*10h - D#_CHCR - DMA Channel Control (Channel 0.6) (R/W)ġF8010F0h - DPCR - DMA Control Register (R/W)ġF8010F4h - DICR - DMA Interrupt Register (R/W)ġF8010F8h (usually 7FFAC68Bh? or 0BFAC688h)ġF8010FCh (usually 00FFFFF7h) (.maybe OTC fill-value)Ĭommonly used DMA Control Register values for starting DMA transfersĬDROM Internal Info on PSX CDROM ControllerĭMA Channels DMA Register Summary 1F80108xh DMA0 channel 0 MDECin (RAM to MDEC)ġF80109xh DMA1 channel 1 MDECout (MDEC to RAM)ġF8010Axh DMA2 channel 2 GPU (lists + image data)ġF8010Bxh DMA3 channel 3 CDROM (CDROM to RAM)ġF8010Dxh DMA5 channel 5 PIO (Expansion Port)ġF8010Exh DMA6 channel 6 OTC (reverse clear OT) (GPU related) ![]()
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